There currently exists no established work flow that allows for communication between an optical proximity correction (OPC) stage, a lithography stage and a masking stage with respect to processing photomasks in designing semiconductor devices. Rather, OPC modeling assumes that a photomask pattern will be equal to the pattern data without considering the masking process such that the verification of an OPC model is based merely on the pattern data. Such OPC modeling will be overly optimistic and prone to failures that could be catastrophic on semiconductor wafer results.
For example, without taking into consideration e-beam forward and backward scattering as well as photomask process effects of development, baking and etching, the resist edge on a photomask will not be the same as a drawn edge. However, OPC modeling that incorporates photomask process correction is not readily transferable to other photomask houses with different photomask writing and etching processes and different fracturing strategies. For example, each photomask house may have a different e-beam writing tool, fracturing algorithm, etching tool, blanks, and resists. Thus, an OPC model with photomask process correction for mask house A may not be usable by mask house B with a different photomask writing and etching tool set for the same photomask performance. Moreover, mask house error budgets are not taken into consideration during OPC model building. Thus, qualifying and analyzing different mask house processes for a particular node is not as straightforward as qualifying wafer results if the mask house printing performance cannot be isolated.
A need, therefore, exists for methodology and an apparatus enabling three-way communication between an OPC stage, a lithography stage, and a masking stage for performing optical proximity and photomask correction.